The present invention relates to a pipeline microprocessor and, more particularly, to an improvement in an instruction decoder unit in a pipeline microprocessor.
In a pipeline microprocessor, respective units, such as an instruction prefetch unit for prefetching an instruction, an instruction decoder unit (IDU) for decoding the prefetched instruction, a memory management unit for calculating an effective address of operand data in response to operand access information from IDU and an execution unit (EXU) for executing the instruction in accordance with decoded instruction information from IDU, perform an individually allocated operation in accordance with a predetermine pipeline flow. IDU is thus decoding an instruction which is a few steps late with respect to an instruction being currently executed by EXU, in general.
A conditional branch instruction is often written in a string of instructions to be executed and is employed to control an instruction stream to be executed according to whether or not a branch condition designated by the conditional branch instruction is satisfied under the content of a program status word controlled by the result and/or state of the instruction executed by EXU. When IDU decodes the conditional branch instruction, it detects the branch condition designated by that instruction. However, if the instruction currently being executed by the EXU and/or a non-executed instruction or instructions between the currently executed instruction and the conditional branch instruction could change the content of the program status word, the branch condition is not settled until EXU completes the execution of such instruction(s).
Therefore, a construction is generally adopted that when IDU decodes the conditional branch instruction it stops to decode subsequent instructions until the branch condition is settled. This means, however, that the pipeline processing flow is suspended effecting the processing-speed of the microprocessor, i.e., the conditional branch instruction disturbs the pipeline processing flow of the microprocessor.